International Research Journal of Innovations in Engineering and Technology - IRJIET International Open Access, Monthly, Peer Reviewed, Reputed Journal ISSN (online): 2581-3048

Impact Factor (2025): 6.9

DOI Prefix: 10.47001/IRJIET

Implementation of an Efficient Vedic Multiplier Incorporating Parallel Prefix Adder Using “Urdhva Tiryagbhyam” Sutra

Abstract

Multiplication is an important fundamental function in any arithmetic operations. A Multiplier is one of the essential hardware blocks in the processor design. Vedic mathematics is a system of mathematics, where the name is given to the ancient Indian mathematic technique which helps to solve the typical mathematical operations in an easy and faster way. Vedic math based multiplier is a high speed multiplier and adder is one of the main component used in the multiplication technique. In this work, a modified Vedic multiplier with high speed that incorporates the fast parallel prefix adder is designed and implemented based on Urdhva Tiryagbhyam (UT) sutra. The performance metrics of proposed Vedic multiplier are achieved and compared with existing Vedic multiplier and conventional multiplier. This Vedic multiplier is designed in Verilog language and simulation is done in Xilinx ISE 14.7. Further, the designed multiplier is applied to image processing applications.

Country : India

1 Rodda Srinivas

  1. Assistant Professor, Department of Electronics and Communication Engineering, Malla Reddy College of Engineering for Women, Hyderabad -500100, Telangana, India

IRJIET, Volume 3, Issue 2, February 2019 pp. 44-50

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