AES-256 Algorithm using FPGA

The rapid increase in the technology has brought up a requirement for more security. This has led to the development of one most secure algorithm for network security called AES algorithm using 256 Bits on FPGA. Advanced Encryption Standard Algorithm (AES) a National Institute of Standards and Technology specifications is an approved cryptographic algorithm that can be used for securing electronic data. Reprogrammable devices such as Field Programmable Arrays (FPGA) are highly attractive option for hardware implementation of cryptographic algorithm AES as they offer a quicker and more customizable solutions. This paper proposes an efficient FPGA implementation of advanced encryption standards (AES). The coding for encryption is done in VHDL language. To implement AES Rijndael algorithm on FPGA offers a better performance than any other cryptographic algorithms. This implementation is covered with other works to show the efficiency. The design uses an iterative looping approach with block and key size of 256 bits, lookup table implementation of S-box. This gives low complexity architecture and easily achieves low latency as well as high throughput.