International Research Journal of Innovations in Engineering and Technology - IRJIET International Open Access, Monthly, Peer Reviewed, Reputed Journal ISSN (online): 2581-3048

Impact Factor (2025): 6.9

DOI Prefix: 10.47001/IRJIET

Investigating Electro-Thermal Coupling in Three-Dimensional Integrated Systems: Simulation Design Advances and Mitigation Strategies

Kifayat UllahSchool of Electrical and Mechanical Engineering, Guilin University of Electronic Technology, Guilin 541004, ChinaAtif Rauf KhanDepartment of Mechanical Engineering Technology, National Skills University, Islamabad, 44000, PakistanNigar HussainSchool of Information and Communication Engineering, Guilin University of Electronic Technology, Guilin 541004, China

Vol 8 No 10 (2024): Volume 8, Issue 10, October 2024 | Pages: 168-177

International Research Journal of Innovations in Engineering and Technology

OPEN ACCESS | Research Article | Published Date: 22-10-2024

doi Logo doi.org/10.47001/IRJIET/2024.810023

pdf iconFull Text PDF
Abstract

Three-dimensional integrated systems employing vertical stacking technology and through-silicon via (TSV) interconnects offer enhanced performance and reduced power consumption. However, TSV technology introduces elector-thermal coupling phenomena, compromising the reliability and efficiency of these systems. This study provides a comprehensive review of simulation design advancements for elector-thermal coupling in TSV-based three-dimensional integrated circuits. Electrical and thermal simulation methodologies are elucidated and potential impacts and mitigation strategies are thoroughly explored. A systematic analysis is presented to elucidate the challenges and optimization opportunities in elector-thermal coupling, informing future research directions.

Keywords

Three dimensional integrated circuits, (3D-ics); through silicon via tsv technology; Electro thermal coupling; simulation design; thermal electric modeling


Citation of this Article

Kifayat Ullah, Atif Rauf Khan, & Nigar Hussain. (2024). Investigating Electro-Thermal Coupling in Three-Dimensional Integrated Systems: Simulation Design Advances and Mitigation Strategies. International Research Journal of Innovations in Engineering and Technology - IRJIET, 8(10), 168-177. Article DOI https://doi.org/10.47001/IRJIET/2024.810023

Licence Copyright (c) 2026 International Research Journal of Innovations in Engineering and Technology creative common licence This work is licensed under Creative common Attribution Non Commercial 4.0 Internation Licence
References
  1. Pedram, M. and S. Nazarian, Thermal modeling, analysis, and management in VLSI circuits: Principles and methods. Proceedings of the IEEE, 2006. 94(8): p. 1487-1501.
  2. Banerjee, K. and A. Mehrotra, Global (interconnect) warming. IEEE Circuits and Devices Magazine, 2001. 17(5): p. 16-32.
  3. Wang, X., et al., The development and progress of multi-physics simulation design for TSV-based 3D integrated system. Symmetry, 2023. 15(2): p. 418.
  4. Fakhreddine, Z., et al., Signal and thermal integrity analysis of 3-d stacked resistive random access memories. IEEE Transactions on Electron Devices, 2020. 68(1): p. 88-94.
  5. Zhou, J.Y., et al. Three-dimensional Simulation of Effects of Electro-Thermo-Mechanical Multi-physical Fields on Cu Protrusion and Performance of Micro-bump Joints in TSVs Based High Bandwidth Memory (HBM) Structures. in 2020 IEEE 70th Electronic Components and Technology Conference (ECTC). 2020.
  6. Belkhiria, M., et al., 2-D-Nonlinear electrothermal model for investigating the self-heating effect in GAAFET transistors. IEEE Transactions on Electron Devices, 2021. 68(3): p. 954-961.
  7. Chai, J., G. Dong, and Y. Yang, Nonlinear electrothermal model for investigating transient temperature responses of a through-silicon via array applied with Gaussian pulses in 3-D IC. IEEE Transactions on Electron Devices, 2019. 66(2): p. 1032-1040.
  8. Chai, J., G. Dong, and Y. Yang, An effective approach for thermal performance analysis of 3-D integrated circuits with through-silicon vias. IEEE Transactions on Components, Packaging and Manufacturing Technology, 2019. 9(5): p. 877-887.
  9. Zhang, H., et al., Modeling, analysis, design, and tests for electronics packaging beyond moore. 2019: Woodhead Publishing.
  10. Zhu, Q., et al., Heat transfer enhancement for microchannel heat sink by strengthening fluids mixing with backward right-angled trapezoidal grooves in channel sidewalls. International Communications in Heat and Mass Transfer, 2022. 135: p. 106106.
  11. Alfellag, M.A., et al., Assessment of heat transfer and pressure drop of metal foam-pin-fin heat sink. International Journal of Thermal Sciences, 2021. 170: p. 107109.
  12. Ding, B., et al., A novel thermal management scheme for 3D-IC chips with multi-cores and high power density. Applied thermal engineering, 2020. 168: p. 114832.
  13. Ding, B., et al., Coupling management optimization of temperature and thermal stress inside 3D-IC with multi-cores and various power density. International Communications in Heat and Mass Transfer, 2021. 120: p. 105021.
  14. Feng, S., et al., Thermal management of 3D chip with non-uniform hotspots by integrated gradient distribution annular-cavity micro-pin fins. Applied Thermal Engineering, 2021. 182: p. 116132.
  15. Feng, S., et al., Heat transfer characteristics investigations on liquid-cooled integrated micro pin-fin chip with gradient distribution arrays and double heating input for intra-chip micro-fluidic cooling. International Journal of Heat and Mass Transfer, 2020. 159: p. 120118.
  16. Kaul, A., et al. Beol-embedded 3d polylithic integration: Thermal and interconnection considerations. in 2020 IEEE 70th Electronic Components and Technology Conference (ECTC). 2020. IEEE.
  17. Xu, Q. and S. Chen, Fast thermal analysis for fixed-outline 3D floorplanning. Integration, 2017. 59: p. 157-167.
  18. Hu, J., et al. Electrical modeling and characterization of through silicon vias (TSV). in 2012 International Conference on Microwave and Millimeter Wave Technology (ICMMT). 2012. IEEE.
  19. Fu, K., et al., Modeling and performance analysis of shielded differential annular through-silicon via (SD-ATSV) for 3-D ICs. IEEE Access, 2018. 6: p. 33238-33250.
  20. Xu, C., et al., Compact AC modeling and performance analysis of through-silicon vias in 3-D ICs. IEEE Transactions on Electron Devices, 2010. 57(12): p. 3405-3417.
  21. Lu, Q., et al., Electrical modeling and characterization of shield differential through-silicon vias. IEEE Transactions on Electron Devices, 2015. 62(5): p. 1544-1552.
  22. Salah, K., et al. Equivalent lumped element models for various n-port Through Silicon Vias networks. in 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011). 2011. IEEE.
  23. Lu, Q., et al., Wideband electromagnetic modeling of coaxial-annular through-silicon vias. IEEE Transactions on Electromagnetic Compatibility, 2017. 60(6): p. 1915-1922.
  24. Savidis, I., et al., Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits. Microelectronics Journal, 2010. 41(1): p. 9-16.
  25. Rao, M. Electrical modeling and characterization of copper/carbon nanotubes in tapered through silicon vias. in 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID). 2017. IEEE.
  26. Hu, Q.-H., et al., Modeling and characterization of differential multibit carbon-nanotube through-silicon vias. IEEE transactions on components, packaging and manufacturing technology, 2020. 10(3): p. 534-537.
  27. Weerasekera, R., et al. Compact modelling of through-silicon vias (TSVs) in three-dimensional (3-D) integrated circuits. in 2009 IEEE International Conference on 3D System Integration. 2009. IEEE.
  28. Katti, G., et al., Electrical modeling and characterization of through silicon via for three-dimensional ICs. IEEE transactions on Electron Devices, 2009. 57(1): p. 256-262.
  29. Kim, J., et al., High-frequency scalable electrical model and analysis of a through silicon via (TSV). IEEE Transactions on Components, Packaging and Manufacturing Technology, 2011. 1(2): p. 181-195.
  30. Dahl, D., et al., Efficient computation of localized fields for through silicon via modeling up to 500 GHz. IEEE transactions on components, packaging and manufacturing technology, 2015. 5(12): p. 1793-1801.
  31. Huang, C., et al. A novel modeling of TSV MOS capacitance by finite difference method. in 2014 15th International Conference on Electronic Packaging Technology. 2014. IEEE.
  32. Xie, B. and M. Swaminathan, FDFD modeling of signal paths with TSVs in silicon interposer. IEEE Transactions on Components, Packaging and Manufacturing Technology, 2014. 4(4): p. 708-717.
  33. Han, K.J., M. Swaminathan, and T. Bandyopadhyay, Electromagnetic modeling of through-silicon via (TSV) interconnections using cylindrical modal basis functions. IEEE Transactions on Advanced Packaging, 2010. 33(4): p. 804-817.
  34. Xie, J. and M. Swaminathan. DC IR drop solver for large scale 3D power delivery networks. in 19th Topical Meeting on Electrical Performance of Electronic Packaging and Systems. 2010. IEEE.
  35. Lan, J.-S. and M.-L. Wu. An analytical model for thermal failure analysis of 3D IC packaging. in 2014 15th International Conference on Thermal, Mechanical and Mulit-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE). 2014. IEEE.
  36. Zhao, Y., C. Hao, and T. Yoshimura, Thermal and wirelength optimization with TSV assignment for 3-D-IC. IEEE Transactions On Electron Devices, 2018. 66(1): p. 625-632.
  37. Huang, P.-Y. and Y.-M. Lee, Full-chip thermal analysis for the early design stage via generalized integral transforms. IEEE transactions on very large scale integration (VLSI) systems, 2009. 17(5): p. 613-626.
  38. Liu, Z., et al., Compact lateral thermal resistance model of TSVs for fast finite-difference based thermal analysis of 3-D stacked ICs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2014. 33(10): p. 1490-1502.
  39. Zhan, Y. and S.S. Sapatnekar, High-efficiency Green function-based thermal simulation algorithms. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2007. 26(9): p. 1661-1675.
  40. Jain, A., et al., Analytical and numerical modeling of the thermal performance of three-dimensional integrated circuits. IEEE Transactions on Components and Packaging Technologies, 2009. 33(1): p. 56-63.
  41. Wang, T.-Y. and C.C.-P. Chen, 3-D thermal-ADI: A linear-time chip level transient thermal simulator. IEEE Transactions on computer-aided design of integrated circuits and systems, 2002. 21(12): p. 1434-1445.
  42. Kuo, W.-S., et al. Thermal investigations of 3D FCBGA packages with TSV technology. in 2008 3rd International Microsystems, Packaging, Assembly & Circuits Technology Conference. 2008. IEEE.
  43. Fu, J., et al. A novel thermal-aware structure of TSV cluster. in 2015 28th IEEE International System-on-Chip Conference (SOCC). 2015. IEEE.
  44. Zhu, J., et al. Fast thermal analysis of TSV-based 3D-ICs by GMRES with symmetric successive over-relaxation (SSOR) preconditioning. in 2015 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS). 2015. IEEE.
  45. Todri, A., et al., A study of tapered 3-D TSVs for power and thermal integrity. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2012. 21(2): p. 306-319.
  46. Hoe, Y.Y.G., et al. Effect of TSV interposer on the thermal performance of FCBGA package. in 2009 11th Electronics Packaging Technology Conference. 2009. IEEE.
  47. Wang, X.-P., W.-s. Zhao, and W.-Y. Yin. Electrothermal modelling of through silicon via (TSV) interconnects. in 2010 IEEE Electrical Design of Advanced Package & Systems Symposium. 2010. IEEE.
  48. Zhao, W.-S., et al. Electrothermal modeling of coaxial through silicon via (TSV) for three-dimensional ICs. in 2010 IEEE Electrical Design of Advanced Package & Systems Symposium. 2010. IEEE.
  49. Katti, G., et al., Temperature-dependent modeling and characterization of through-silicon via capacitance. IEEE Electron Device Letters, 2011. 32(4): p. 563-565.
  50. Wang, X.-P., W.-Y. Yin, and S. He, Multiphysics characterization of transient electrothermomechanical responses of through-silicon vias applied with a periodic voltage pulse. IEEE transactions on electron devices, 2010. 57(6): p. 1382-1389.
  51. Lu, T. and J.-M. Jin, Transient electrical-thermal analysis of 3-D power distribution network with FETI-enabled parallel computing. IEEE Transactions on Components, Packaging and Manufacturing Technology, 2014. 4(10): p. 1684-1695.
  52. Lu, T. and J.-M. Jin, Thermal-aware high-frequency characterization of large-scale through-silicon-via structures. IEEE Transactions on Components, Packaging and Manufacturing Technology, 2014. 4(6): p. 1015-1025.
  53. Lu, T. and J.-M. Jin, Electrical-thermal co-simulation for DC IR-drop analysis of large-scale power delivery. IEEE Transactions on Components, Packaging and Manufacturing Technology, 2013. 4(2): p. 323-331.
  54. Sai, M.P., et al., Reliable 3-D clock-tree synthesis considering nonlinear capacitive TSV model with electrical–thermal–mechanical coupling. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2013. 32(11): p. 1734-1747.
  55. Jiang, L., et al., A thermal simulation process based on electrical modeling for complex interconnect, packaging, and 3DI structures. IEEE transactions on advanced packaging, 2010. 33(4): p. 777-786.
  56. Chen, Y., et al., Through silicon via aware design planning for thermally efficient 3-D integrated circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2013. 32(9): p. 1335-1346.
  57. Saha, D. and S. Sur-Kolay, Guided GA-based multiobjective optimization of placement and assignment of TSVs in 3-D ICs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019. 27(8): p. 1742-1750.
  58. Grzesiak-Kopeć, K., P. Oramus, and M. Ogorzałek, Hypergraphs and extremal optimization in 3D integrated circuit design automation. Advanced Engineering Informatics, 2017. 33: p. 491-501.
  59. Satomi, Y., et al., Thermal placement on PCB of components including 3D ICs. IEICE Electronics Express, 2020. 17(3): p. 20190737-20190737.
  60. Srikanth, R., P. Nemani, and C. Balaji, Multi-objective geometric optimization of a PCM based matrix type composite heat sink. Applied energy, 2015. 156: p. 703-714. 

Copyright @ 2026 IRJIET. All Right Reserved.

Licensed underCreative Commons Attribution 4.0 International License.