Profile-Aware Parasitic Extraction of Tapered Through-Glass Vias: Quantifying the Validity of the Ideal-Cylinder Compact Model

Through-glass vias (TGVs) are the vertical interconnect of choice for emerging glass-substrate 2.5-D and 3-D packaging, yet fabricated vias are not ideal cylinders: laser and etch-based processes leave a tapered profile, while the compact equivalent-circuit models used in fast channel simulation almost universally assume a straight cylindrical via. This work quantifies, from full-wave simulation, how the extracted parasitics of a coaxial TGV depend on taper and establishes the range over which the ideal-cylinder assumption remains accurate. A parametric three-dimensional model is solved with a full-wave transient solver over a factorial sweep of taper ratio, top diameter, and glass thickness; series resistance and inductance and shunt capacitance are extracted from the simulated admittance parameters using an asymmetry-robust formulation. A Gaussian-process surrogate trained on the resulting dataset reproduces the full-wave parasitics under leave-one-out cross-validation with a coefficient of determination of at least 0.97, enabling dense exploration of the design space at negligible cost. The series inductance increases monotonically as the via tapers, by about thirteen percent over the studied range, and the ideal-cylinder model is shown to remain within a ten percent inductance error only down to a taper ratio of about 0.68, below which a profile-aware correction is required.