International Research Journal of Innovations in Engineering and Technology - IRJIET International Open Access, Monthly, Peer Reviewed, Reputed Journal ISSN (online): 2581-3048

Impact Factor (2025): 6.9

DOI Prefix: 10.47001/IRJIET

Modeling of CMOS-MTJ Hybrid Full Adder Circuit for Ultra-Low Power Architectures

Abstract

A novel design of adiabatic CMOS-MTJ hybrid full adder circuit is designed in this paper. Low power designs are essential with the increasing demand of IOT based portable devices in the market. Logic in memory architecture using spintronic devices along with multi-threshold CMOS circuits is an innovative idea to reduce the usual static and dynamic power dissipation in VLSI circuits. Magneto Electric Magnetic Tunnel Junction (ME MTJ) is an emerging spintronic technology, which shows good compatibility with VLSI circuits. This emerging technology is of great interest to overcome the issues such as volatility, power consumption, switching delay etc. Thus, we propose a 14T Multi-threshold CMOS & Magneto-electric MTJ hybrid full adder circuit. The circuit is simulated using National Instruments CIRCUIT DESIGN SUIT. The proposed adiabatic MT CMOS-ME MTJ full adder circuit can replace traditional 28T full adder circuit and enables logic in memory architecture in ultra-low power applications.

Country : India

1 Greeshma2 Mahitha M. Das3 Greshma Mohan4 Ajin A. S

  1. Student, Dept of ECE, Ahalia School of Engineering and Technology, Kerala, India
  2. Student, Dept of ECE, Ahalia School of Engineering and Technology, Kerala, India
  3. Student, Dept of ECE, Ahalia School of Engineering and Technology, Kerala, India
  4. Assistant Professor, Dept of ECE, Ahalia School of Engineering and Technology, Kerala, India

IRJIET, Volume 2, Issue 1, March 2018 pp. 20-23

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References

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