Low-Power Split-Radix FFT Processors Using Dual Edge Triggered Flip Flop

Well-known Fast Fourier Transform (FFT) is the most common signal processing algorithm for observing the frequency contents of incoming signals in telecommunication transceivers. It is notably used in cognitive or software defined radio which usually demands for monitoring the spectrum in a wide frequency band. This may imply heavy computation burde non processors when the ordinary FFT algorithm is implemented, and hence yield considerable power consumption. Split-radix fast Fourier transform (SRFFT) is an ideal candidate for the implementation of a low-power FFT processor, because it has the lowest number of arithmetic operations among all the FFT algorithms. In the design of such processors, an efficient addressing scheme for FFT data as well as twiddle factors is required. The signal flow graph of SRFFT and the radix-2 FFT is same. Therefore, the generation of conventional address of FFT could also be applied to Split-radix fast Fourier transform (SRFFT). Dual edge triggered flip flop (DETFF) instead of using single edge triggered flip flop traditionally in the architecture improves speed level and decreases power consumption by using DETFF, it propagate  and captures the data at both clock edges hence it is suitable for high speed of FFT module can be increased the high data rate applications.